A) Technical Field
The present invention relates to memory devices capable of high speed serial data transfer to a peripheral device, such as a raster display.
B) Background Art
Video Random Access Memories (VRAMs) are a type of memory commonly used in video displays for computer systems. A VRAM is essentially a conventional dynamic random access memory (DRAM) with the addition of a second port where data may be accessed serially. A VRAM consists of a random access memory (RAM) portion and a serial access memory (SAM) portion with transfer gates which allow data to pass between the RAM and the SAM. The SAM array usually has the memory capacity of one row of the RAM array. A full row of memory data may be passed between RAM and SAM in a single data transfer access. The RAM port and the SAM port may be operated asynchronously and independently except when the data transfer between the RAM and the SAM is taking place.
This independent and asynchronous operation of the two ports finds application in the video displays of computer systems where the RAM port is used to update the contents of display memory and the serial port is used to provide data to be rastered onto the display. The RAM port may be operated at the frequency of the computer system and the SAM port at a frequency dictated by the requirements of the raster display Since the SAM array usually has the capacity of a single row of display data, it must be continually reloaded with new rows of display data during the time of the display frame. In general, each new row of display data is obtained from a row whose index is one greater than that of the previous row. The reloading of the SAM array with new rows of display data from the RAM array is achieved by performing data transfer cycles at the RAM port. These data transfer cycles between the RAM array and the SAM array are the only interruption to the normal RAM access cycles at the RAM port. They may be separated into two distinct types. The first is data transfer when the SAM port is inactive, with no data passing to the raster display and with the serial clock stopped. This is usually associated with reloading of the SAM during blanking of the display frame. The second is data transfer when the SAM port is active, with data passing to the raster display. Since in this case the serial clock is running, the data transfer cycle at the RAM port requires accurate synchronization with the serial clock in order to maintain the required seamless flow of data to the raster display from the SAM port. This second situation is often referred to as "Real-Time Data Transfer" or "Mid-Line Reload."
In the design of a display memory subsystem, the control and timing of such mid-line reloads presents a major problem. A "Mid-Line Reload" is a critically timed real-time access, requiring synchronization between the RAM and the SAM ports, and can be very wasteful of RAM port bandwidth, a crucial aspect in many display memory subsystems. Additionally, such critically timed real time accesses may require potentially complex and high-speed circuitry to synchronize and control them. Thus, workers in the art have attempted to completely avoid mid-line reloads, so as to circumvent the critical timings and/or complex circuitry associated therewith. The conventional method of avoiding mid-line reloads involves a number of restrictions upon how the contents of display memory are mapped onto the display screen. These restrictions include the following:
(1) use of a fixed start address for the display data on the first horizontal scan line of the display frame; PA1 (2) use of a fixed address increment to generate the start address of each subsequent horizontal scan-line; and PA1 (3) use of a horizontal scan-line length which requires an amount of display data not greater than the capacity of the SAM arrays of the VRAMs in the display memory subsystem.
In the prior art, all of these restrictions must be satisfied in order to avoid a mid-line reload. Note that these restrictions cannot be applied to a general purpose graphics adapter or display memory subsystem.
Second generation VRAMs were enhanced with the ability to transfer half a row of random access memory into half of the SAM while the other half of the SAM is being scanned out to the display. This means of avoiding real-time data transfers is found in a 1M bit multiport DRAM manufactured by the Toshiba Corporation, and is generally described in U.S. Pat. Nos. 4,825,411 and 4,855,959. In these so-called "Split Register" VRAMs, the SAM array divided into two halves, either of which can be loaded independently by so-called "Split Register Data Transfers" whereby one half of the SAM is loaded while the other half is active. Typically an output status pin is provided to indicate the half of the SAM being scanned out.
While split-register VRAMs alleviate mid-line reloads to some extent, they do not make full and efficient use of the SAM array capacity and can potentially result in twice as many data transfer accesses.